Bad information for anybody seeking to get their arms on Nvidia’s prime specced GPUs, such because the A100 or H100: it isn’t going to get any simpler to supply the components till not less than the tip of 2024, TSMC has warned.
The drawback, it appears, is not that TSMC – which fabricates not simply these GPUs for Nvidia but in addition parts for AMD, Apple, and plenty of others – cannot make sufficient chips. Rather, an absence of superior packaging capability used to sew the silicon collectively is holding up manufacturing, TSMC chairman Mark Liu instructed Nikkei Asia.
(*18*) to Liu, TSMC is barely capable of meet about 80 p.c of demand for its chip on wafer on substrate (CoWoS) packaging know-how. This is utilized in a number of the most superior chips in the marketplace as we speak – significantly people who depend on high-bandwidth reminiscence (HBM) which is good for AI workloads.
Liu expects this can be a short-term bottleneck within the manufacturing of machine-learning accelerators and that further CoWoS capability ought to come on-line inside a yr and a half. Incidentally, TSMC just lately introduced plans to broaden its superior packaging capability in Taiwan with a $3 billion facility on the Tongluo Science Park in Miaoli County.
Until TSMC can deliver further capability on-line, Nvidia’s H100 and older A100 – which energy many in style generative AI fashions, reminiscent of GPT-4 – are on the coronary heart of this scarcity. However, it isn’t simply Nvidia. AMD’s upcoming Instinct MI300-series accelerators – which it confirmed off throughout its Datacenter and AI occasion in June – make intensive use of CoWoS packaging know-how.
AMD’s MI300A APU is at the moment sampling with prospects and is slated to energy Lawrence Livermore National Laboratory’s El Capitan system, whereas the MI300X GPU is because of begin making its means into prospects’ arms in Q3.
We’ve reached out to AMD for touch upon whether or not the scarcity of CoWoS packaging capability may affect availability of the chip and we’ll let you already know if we hear something again.
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It’s value noting that TSMC’s CoWoS is not the one packaging tech on the market. Samsung, which is rumored to choose up a number of the slack for the manufacturing of Nvidia GPUs, has I-Cube and H-Cube for two.5D packaging and X-Cube for 3D packaging.
Intel, in the meantime, packages a number of of the chiplets utilized in its Ponte Vecchio GPU Max playing cards, however would not depend on CoWoS tech to sew them collectively. Chipzilla has developed its personal superior packaging tech, which might work with chips from completely different fabs or course of nodes. It’s referred to as embedded multi-die interconnect bridge (EMIB) for two.5D packaging and Foveros for vertically stacking chiplets on prime of 1 another. ®
…. to be continued
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